Release Notes for  STM32U5xx CMSIS

Copyright © 2021 STMicroelectronics

Update History

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Update STM32U5A5xx devices list with STM32U5A5QII3Q under “stm32u5xx.h” file

Backward Compatibility

  • N/A

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Support of new STM32U5F9xx, STM32U5G9xx, STM32U5F7xx and STM32U5G7xx devices:
    • Add “stm32u5f9xx.h”, “stm32u5g9xx.h”, “stm32u5f7xx.h” and “stm32u5g7xx.h” files
    • Add startup files “startup_stm32u5f9xx.s”, “startup_stm32u5g9xx.s”, “startup_stm32u5f7xx.s” and “startup_stm32u5g7xx.s” for EWARM, STM32CubeIDE and MDK-ARM toolchains
    • Add linker files for EWARM and STM32CubeIDE toolchains of STM32U5F9xx/STM32U5G9xx/STM32U5F7xx/STM32U5G7xx devices

Backward Compatibility

  • N/A

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Support of stm32u535xx and stm32u545xx devices:
    • Add “stm32u535xx.h” and “stm32u545xx.h” files
    • Add startup files “startup_stm32u535xx.s” and “startup_stm32u545xx.s” for EWARM and STM32CUBEIDE toolchains
    • Add EWARM and STM32CUBEIDE linker files for all devices for legacy and for TrustZone based application
  • Registers and bit field definitions updates:

    • Add USB Dual Role Device FS Endpoint registers:
      • Add Bits definition for USB_DRD_CNTR register
      • Add Bits definition for USB_DRD_ISTR register
      • Add Bits definition for USB_DRD_FNR register
      • Add Bits definition for USB_DRD_DADDR register
      • Add Bit definition for USB_DRD_BTABLE register
      • Add Bit definition for LPMCSR register
      • Add Bits definition for USB_DRD_BCDR register
      • Add Bits definition for USB_DRD_CHEP register
    • Add USB_IRQn interrupt
    • Add USB_OTG_GCCFG_PULLDOWNEN define
    • Add LSECSSD and MSI_PLL_UNLOCK global interrupts
    • Add USART_DMAREQUESTS_SW_WA define
    • Add DBGMCU_APB1FZR2_DBG_I2C5_STOP and DBGMCU_APB1FZR2_DBG_I2C6_STOP defines
    • Remove DBGMCU_APB1FZR2_DBG_FDCAN_STOP define
    • Add AES_IER_RNGEIE AES_ICR_RNGEIF and AES_ISR_RNGEIF defines
    • Add DMA2D_TRIGGER_SUPPORT define
    • Rename Bit definition for EXTI_SECENR1 register to EXTI_SECCFGR1 register
    • Rename Bit definition for EXTI_PRIVENR1 register to EXTI_PRIVCFGR1 register
    • Add Bit definition for EXTI_LOCKR register
    • Add EXTI_RTSR1_RT25, EXTI_FTSR1_FT25, EXTI_SWIER1_SWI25, EXTI_RPR1_RPIF25, EXTI_FPR1_FPIF25, EXTI_IMR1_IM25 and EXTI_EMR1_EM25 defines
    • Add COMP_WINDOW_MODE_SUPPORT define
    • Add Bit definition for SYSCFG_OTGHSPHYTUNER2 register
    • Add SYSCFG_CFGR1_SRAMCACHED define
    • Add UCPD configuration register 3
    • Add RCC_APB2RSTR_USBRST define
    • Add RCC_APB2ENR_USBEN define
    • Add RCC_APB2SMENR_USBSMEN define
    • Add IS_SPI_GRP1_INSTANCE and IS_SPI_GRP2_INSTANCE macros
    • Add IS_COMP_ALL_INSTANCE macro
    • Add IS_HCD_ALL_INSTANCE and IS_PCD_ALL_INSTANCE macro
    • Add PWR_CR1_FORCE_USBPWR and PWR_VOSR_VDD11USBDIS defines
    • Rename OCTOSPI_CR_DQM to XSPI_CR_DMM
    • Rename OCTOSPI_CR_FSEL to XSPI_OCTOSPI_CR_MSEL
    • Rename ADC4_PW_AUTOFF to ADC4_PWRR_AUTOFF
    • Rename ADC4_PW_DPD to ADC4_PWRR_DPD
    • Rename ADC4_PW_VREFPROT to ADC4_PWRR_VREFPROT
    • Rename ADC4_PW_VREFSECSMP to ADC4_PWRR_VREFSECSMP

Backward Compatibility

  • N/A

Main Changes

  • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
    • Add the support of STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices
    • Define XSPI_TypeDef as alias to OCTOSPI_TypeDef and HSPI_TypeDef
    • Define XSPIM_TypeDef as alias to OCTOSPIM_TypeDef
    • Update XSPI bit definition to alias OCTOSPI and HSPI bits
    • Add OPAMP12_COMMON_NS, OPAMP12_COMMON_S, OPAMP12_COMMON, OPAMP12_COMMON_BASE defines
    • Update OPAMP_Common_TypeDef to align with reference manual
    • Add the SRAM4 memory definition in all STM32CubeIDE flashloader files
    • Update the flash size define to support:
      • STM32U575/STM32U585: 2Mbytes flash devices
      • STM32U595/STM32U5A5/STM32U599/STM32U5A9: 4Mbytes flash devices
    • Rename PVD_AVD_IRQHandler to PVD_PVM_IRQHandler in all start-up files
    • Rename RCC_AHB2RSTR1_ADC1RST to RCC_AHB2RSTR1_ADC12RST
    • Rename RCC_AHB2ENR1_ADC1EN to RCC_AHB2ENR1_ADC12EN
    • Rename RCC_AHB2SMENR1_ADC1SMEN to RCC_AHB2SMENR1_ADC12SMEN
    • Rename RCC_CCIPR1_CLK48MSEL to RCC_CCIPR1_ICLKSEL
    • Rename RCC_SECCFGR_CLK48MSEC to RCC_SECCFGR_ICLKSEC
    • Add TIM3 and TIM4 are missing in IS_TIM_32B_COUNTER_INSTANCE macro definition

Main Changes

  • Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define
  • Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define
  • Add LSI_STARTUP_TIME define
  • Fix wrong IRQn name in partition_stm32u5xx.h

Main Changes

  • First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)